Asynchronous Processor Design Using Higher-Order Petri Nets

Mustsfa Sami 1, Ali Mohammed Meligy2, Azez Shafik3 and Musaad Wageh Hassan4
1 Professor of Computer Science, Helwan University
2 Associate Professor of Computer Science, Menoufya University
3Lecturer of Mathematics, Menoufya University
4Ass. Lecturer of Computer Science, Tanta University
 

Abstract:
This paper presents an approach for designing an asynchronous processor using higher-order Petri nets (HOPN). HOPNs form a new class of Petri nets that exploits the properties of higher-order neural networks. The concepts of higher-order arcs will be applied in order to model accurate circuit properties, such as timing information, connection, and concurrency. We consider HOPNs with transitions that have indegree < 1. As a prototype for our design approach we use Holton’s Processor. We follow the top-down design, in which we refine the top-level specification until we reach to the implementable level. For analyzing the HOPN, a theorem on the relationship between the potential firability of the goal transition and T-invariant is proved. The circuit synthesis corresponding to the HOPN is discussed.
Keywords: Petri nets (PN), higher-order Petri nets (HOPN), Processor design, Holton’s processor model.